1. Field of the Invention
The present invention relates to an information processing apparatus having a pseudo static random access memory (hereinafter, referred to as PSRAM). More particularly, the invention relates to an information processing apparatus that performs refresh to maintain the data of PSRAM.
2. Description of the Prior Art
In recent years, the PSRAM has been used for rapidly increasing numbers of applications as a device having both the feature of large capacity and low price by virtue of its memory cell array architecture similar to and as simple as that of a dynamic random access memory (DRAM), and the feature of simplicity in interface by adopting the non-multiplex addressing system similar to that of a static random access memory (SRAM). However, because of the memory cell array architecture similar to that of DRAM, the PSRAM needs to be subjected to the operation of so-called refresh periodically (every few milliseconds to few tens milliseconds, the period differing from memory to memory) in order to maintain data.
The mode of refresh operation for the PSRAM can be classified roughly into two types, auto-refresh mode and self-refresh mode. In the auto-refresh mode, a CPU (Central Processing Unit) discriminates a period in which the PSRAM is not accessed, and makes the PSRAM refreshed based on a clock during the period. On the other hand, in the self-refresh mode, the PSRAM itself performs refresh irrespectively of the clock. As a result, the refresh is performed even with the clock halted.
Conventionally, the PSRAM has actually been refreshed by such a system as shown in FIG. 18. In response to control signals S4, S5 from a CPU 901 for instructing the operation and halt of the system clock, an oscillation controller 906 generates a signal STP. Responsively to the level of the signal STP, either "H" (High) or "L" (Low), a CPU system clock generator 903 oscillates or stops oscillation. An output of the oscillation controller 906 and an output of the CPU system clock generator 903 are combined together by a NOR circuit 991 to generate a system clock CG1. A count clock generator 904 is normally generating a count clock CG2. The frequency of the system clock CG1 is set far higher than that of the count clock CG2. A refresh controller 905 controls address refresh and auto-refresh in response to control signals S1, S2, respectively, fed from the CPU 901. A control signal S3 from the CPU 901 and a chip-enable signal CE# fed from the CPU 901 via the refresh controller 905 are combined together by an OR circuit 992 and inputted to a CE# terminal of PSRAM 902. Also, a signal obtained by delaying the control signal S3 derived from the CPU 901 by a time that depends on the CR time constant of a delay circuit 907, and a refresh signal RFSH# fed from the CPU 901 via the refresh controller 905 are combined together by a NOR circuit 993 and inputted to a RFSH# terminal of the PSRAM. When the CE# (# representing inversion; alike hereinafter) terminal and RFSH# terminal of the PSRAM 902 are maintained "H" and "L", respectively, for a specified time interval or more, the PSRAM 902 is set to the self-refresh mode.
However, in the above-described system, if the CPU system clock 903 comes to a halt for some reason (abnormal halt) without setting the PSRAM 902 to the self-refresh mode, the PSRAM 902 remains unrefreshed for a certain time interval or more so that the storage contents of the PSRAM 902 will be lost, disadvantageously.